1. Field of the Invention
The present invention relates to an embedded inductor, and more particularly, to a package applying this embedded inductor.
2. Description of the Related Art
In general, the conventional wiring board for hosting and electrically connecting a plurality of electronic devices is mainly composed of a plurality of patterned conductive layers and a plurality of insulating layers that are disposed alternately with each other. The patterned conductive layers may be formed by performing a patterning process on the copper foil, and the insulating layers are disposed between the neighboring patterned conductive layers in order to insulate the patterned conductive layers from each other. In addition, the interleaved conductive layers are electrically connected with each other through the conductive vias passing through the insulating layers. Moreover, various electronic devices (for example, active or passive devices) may be further
The passive device mentioned above may be a capacitor, a resistor, or an inductor. Such types of passive device can be disposed on the surface of the wiring board by the Surface Mount Technology (SMT). In addition, the passive device also can be embedded in the wiring board in order to increase the layout area of the wiring board. Please refer to FIGS. 1A and 1B for the details of the embedded inductor. FIG. 1A is a perspective view of a conventional embedded inductor suitable for a wiring board, and FIG. 1B is a cross sectional view along line A-A in FIG. 1A. The conventional embedded inductor 100 is suitable for a wiring board 10. The wiring board 10 comprises four patterned conductive layers 12, three insulating layers 14, and a plurality of conductive vias 16 (only one conductive via is shown in FIG. 1B). A top patterned conductive layer 12a forms a conductive spiral structure 110 of the embedded inductor 100, and a conductive line 112 of the conductive spiral structure 110 forms a spiral pattern. Moreover, one end of the conductive line 112 is electrically connected to a bottom patterned conductive layer 12d through a conductive via 16. Furthermore, the patterned conductive layers 12b and 12c are used as a power plane and a ground plane, respectively.
However, a parasitic capacitance effect will occur during operating the conventional embedded inductor, which decreases the self-resonance frequency of the embedded inductor. Moreover, the quality factor Q of the embedded inductor is further degraded due to the dielectric loss of the insulating layers in the wiring board. Accordingly, how to reduce the parasitic capacitance value of the conventional embedded inductor becomes a major issue in the field.